This invention relates generally to semiconductor integrated circuits formed of CMOS technology and more particularly, it relates to an improved self-boost circuit which has a faster speed of operation and has a higher logic "1" output voltage level than has been traditionally available.
It is often necessary and/or desirable to operate different parts of an electronic system at different voltage levels. At the places where the different parts interface, they must be coupled to each other. However, the signals at the interfaces are not necessarily compatible. It is therefore at times necessary to provide interface and driver output buffer circuits so as to render one part of the system to be compatible with another part, such as is required when driving large loads. Typically, such driver output buffer circuits include a pull-up device connected between an upper power supply potential VDD and an output node and a pull-down device connected between a lower power supply potential VSS and the output node. Sometimes, a P-channel device is provided so as to function as the pull-up device for generating a high output voltage level V.sub.OH corresponding to the high logic level.
However, in applications which require high drive capability the P-channel pull-up devices have been replaced with N-channel devices because their intrinsic mobility is more than twice than that of the P-channel device. With its greater mobility, the N-channel device is twice as conductive as compared to the P-channel device of an equal size. Due to its greater conduction, the N-channel device will have only half of the impedance between the drain terminal and the source terminal than an equivalent P-channel device. When such N-channel devices are utilized as the pull-up devices, they operate like source followers. In other words, the source electrode of the N-channel devices will attempt to follow the voltage at its gate electrode. The only disadvantage in using the N-channel devices is that the source electrode can only be pulled up to a voltage which is a threshold drop below the gate voltage.
In FIG. 1, there is shown a conventional source follower circuit 2 which includes an N-channel pull-up transistor MN1. The drain of the transistor MN1 is connected to an upper power supply potential VDD, which is approximately +5.0 volts. The gate of the transistor MN1 is connected to an input node 4 for receiving an input control signal ENHIGH. The source of the transistor MN1 is connected to an output node 6 for providing an output. As is generally well-known in CMOS digital integrated circuits, the input control signal ENHIGH has normal logic levels which are (1) a low or "0" logic state represented by a lower power supply potential VSS and (2) a high or "1" logic state represented by the upper power supply potential VDD. The lower power supply potential VSS is usually connected to an external ground or 0 volts. Thus, if the gate voltage on the node 4 is restricted to operate within the CMOS (0 to +5.0 volts) range then the N-channel source follower circuit can only pull up the output node 6 to a voltage of +5.0 volts minus a threshold voltage V.sub.Tn or approximately +3.5 volts. The voltage V.sub.Tn is the body-effect enhanced threshold of the N-channel transistor MN1 which is variable dependent upon the operating voltage of the source electrode relative to the voltage applied to the substrate.
This threshold voltage can be fixed by connecting the N-channel substrate to the source electrode. However, this technique is only permitted in CMOS technologies in which the N-channel devices have isolated p-well substrates. It will be noted that if it is desired to adhere to TTL output logic levels then the conventional source follower circuit 2 is quite adequate since the output node 6 needs to be pulled up only to the voltage of approximately +2.4 volts. On the other hand, if higher output voltage levels are required, i.e., CMOS logic levels of 0 to +5.0 volts, then either the gate voltage must be increased or the threshold voltage must be reduced. Since the reduction of the device threshold voltage will have an adverse effect on other circuits, this procedure is usually never performed.
There has been attempted in the prior art of increasing the gate voltage by utilizing a gate boosting circuit 8 as illustrated in FIG. 2. The boosting circuit 8 includes an additional second N-channel transistor MN2. The transistor MN2 has its gate connected to the upper power supply potential VDD and its source connected to the input node 4 for receiving the input control signal ENHIGH. The drain of the transistor MN2 is connected to the gate (node NUP) of the N-channel pull-up transistor MN1. A sel.-capacitance SC, defining a parasitic capacitance, is connected between the gate node NUP and the output node 6. The transistor MN2 provides isolation between the input control signal ENHIGH and the gate node NUP when the signal ENHIGH is asserted (a high logic level).
As the input control signal ENHIGH is making the low-to-high transition, the transistor MN2 does not turn off until the input control signal ENHIGH reaches approximately +3.5 volts due to again the body-effect threshold. At this point, the self-capacitance pushes the gate node NUP higher as the voltage on the source of the transistor MN1 rises, which is actually when the boosting effect begins. Accordingly, this self-boosting circuit 8 having a starting voltage of approximately +3.5 volts suffers from the disadvantage of providing a voltage rise at the gate node NUP which is actually slower than the input control signal ENHIGH provided to the gate of the conventional source follower circuit 2 of FIG. 1. Therefore, while the boosting circuit 8 will generate a higher final output voltage level corresponding to the high logic level, it has a slower speed of operation.
It would therefore be desirable to provide an improved self-boost circuit which not only provides a higher logic "1" output voltage level but also has a faster switching speed. The present self-boost circuit represents an improvement over the conventional self-boosting circuit of FIG. 2.